The present invention relates to a semiconductor integrated circuit device and, more particularly, to improvements in a circuit for applying a potential to a back gate of a MOS transistor. As is well known in the art, such as in NAND, NOR and EXOR gate, a P-channel MOS transistor in an N-well formed in a P-type substrate and an N-channel MOS transistor in a P-well formed in an N-type substrate can have source potentials different from the supply potential. Such an arrangement is also used with the MOS transistors which construct the differential amplifiers in an operational amplifier. In the conventional circuits, these MOS transistors have had their back gates (i.e., the wells insulated from the substrate) set at the same potential as the source, that is, at the highest potential in the case of P-channel MOS transistors, or at the lowest potential in the case of N-channel MOS transistors.
In a circuit in which the source potential is applied to the back gate of the MOS transistor by connecting the back gate directly to the source electrode, however, the large capacitance between the well forming the back gate and the substrate is applied to the source electrode. As a result, if the source potential fluctuates, the time period for charging or discharging this capacitance is elongated to invite a reduction in the switching speed.
In the circuit in which the back gate is connected to the source electrode, moreover, there arises another defect in that the substrate bias effect causes the threshold voltage to increase with an increase in the reverse bias voltage between the source electrode and the back gate.